This invention relates generally to integrated circuit (IC) fabrication processes and, more specifically, to a chemical-mechanical polish (CMP) slurry that permits the planarization of noble metals, and the formation of noble metal damascene electrode structures.
CMP processes are designed to polish IC surfaces in a mass production fabrication environment to a flatness in the range of approximately 50 to 1500 .ANG., across a wafer surface. CMP processes are often performed after metalization steps. A deposited metal film must be planarized in some wafer areas, while the metal is entirely removed in other regions of the wafer. Thus, metal, as well as silicon, silicon oxide, and various other dielectric materials may be removed simultaneously without contaminating or damaging the underlying wafer surface.
In many commercial processes, interconnection metals such as Al or W are deposited as a film on a wafer surface through physical vapor deposition (PVD) or sputtering. Interconnection lines across a wafer surface, or vias to subsequently formed overlying IC metal levels, are formed by pattern etching to remove the undesired areas of the metal film. Oxide is typically used to insulate around the metal interconnections. Upon completion of an IC level, a CMP process is performed to render the surface planar.
Platinum (Pt) and other noble metals are used in IC structure ferroelectric capacitors. The use of noble metals is motivated by their inherent chemical resistance. This property is especially desirable under high temperature oxidation conditions, such as those seen in the fabrication of ferroelectric capacitors. In addition, chemical interaction between noble metals and ferroelectric materials such as perovskite metal oxides, is negligible.
However, the pattern etching of noble metals, whether done through wet or dry processes, can be problematic. Etching tends to lead to poor pattern definition. For example, the resultant metal structure often have sloped, instead of vertical, walls. Etching processes also leave chemical residues, and even a CMP process cannot remove residues from vertical sidewall structures.
Metal structures can also be patterned and formed through damascene techniques. A dielectric film is formed first. The dielectric is pattern etched to form inlays. Then, metal is deposited over the dielectric, filling the inlays and forming a film over the dielectric. A CMP process removes the overlying metal film, leaving the metal-filled inlays intact.
Commercial equipment is readily available to perform CMP processes. FIG. 1 illustrates an apparatus to perform a CMP process (prior art). CMP apparatus 10 includes a rotating table pad 12 and a rotating wafer mounting pad, or spindle 14. Typically, the wafer 16 to be polished is mounted, upside down, on a rotating spindle 14. Polishing pad 12 is also rotated. Polishing pad 12 is typically a commercially available polyester/polyurethane material. A slurry is introduced, through port 18, between rotating table pad 12 and wafer holder 14. The chief variables in the polishing process are the relative rotation rates of pad 12 and holder 14, the pressure between wafer 16 and pad 12, the time duration of the process, and the type of slurry used.
As the title implies, the CMP process removes materials from a wafer surface through both a chemical reaction and physical abrasion. In a typical CMP process the slurry contains a chemical agent which is an etchant, or modifier, selective to the material to be removed. The chemical agent acts to chemically dissolve the wafer surface, while the abrasive acts to remove the modified material from the wafer surface. When potassium hydroxide is used as the etchant and silica as the abrasive, such as slurry is effective for the polishing of silicon, silicon dioxide, and silicon nitride.
Several slurry compounds have been developed for the removal of Al, W, copper, Si, SiO.sub.2, Si.sub.3 N.sub.4, etc. However, no effective slurries are available for the removal of noble metals in a CMP process. The same qualities that make noble metal effective electrical conductors, make them resistant to chemical reaction and, therefore, difficult to etch. Even if deposition procedures are developed for noble metals, the lack of effective CMP procedures, especially effective slurries, prevent noble metal electrodes or interconnects to be used current IC designs.
It would be advantageous if a CMP process slurry were developed for the planarization of noble metals.
It would be advantageous if a slurry were developed that permitted noble metals to be planarized in standard CMP processes, using standard commercially available CMP equipment.
It would be advantageous if the advent of noble metal CMP processes permitted the formation of noble metal structures using damascene, or dual damascene deposition techniques.
Accordingly, a chemically active slurry to polish noble metals has been provided. The slurry comprises an elemental halogen in a strongly basic aqueous solution as the chemical agent, in addition to an abrasive. The elemental halogen may be either bromine, iodine, or chlorine, although bromine is preferred. The aqueous solution base may be either sodium hydroxide (NaOH), potassium hydroxide (KOH), tetramethyl ammonium hydroxide ((CH.sub.3).sub.4 NOH), or a generic tetraalkyl ammonium hydroxide (R.sub.4 NOH), but NaOH is preferred. Specifically, 1.3 mols of bromine (Br.sub.2) is combined with 0.5 mols of sodium hydroxide (NaOM), in 500 ml of pure water, to form a sodium hydroxide and bromine solution.
The abrasive may be either aluminum oxide (Al.sub.2 O.sub.3), CeO.sub.2, or SiO.sub.2. When the abrasive is (Al.sub.2 O.sub.3), it is mixed with water to form an aluminum oxide suspension including from 1 to 50% aluminum oxide by weight. Then, 5 parts, by volume, of sodium hydroxide and bromine solution are combined with 1 part of the aluminum oxide suspension.
A method of polishing, using a standard CMP process polishing table pad, is also provided. The method comprises the steps of:
a) placing a surface of noble metal in interaction with the polishing pad; PA1 b) introducing a slurry, including an elemental halogen in a strongly basic aqueous solution and an abrasive, interposed between the table pad and the noble metal; and PA1 c) in response to Steps a) and b), chemically polishing the noble metal surface. In some aspects of the invention, Pt is removed from the surface at a rate of 1800 .ANG./min. A force of approximately 4 PSI between the metal surface and the table pad, and a polishing pad/spindle rotation rates of approximately 40 RPM is typical.
This CMP process is effective with the use noble metals selected from the group consisting of Pt, Ir, Ru, Pd, Ag, Au, Os, and Rh. It is expected that Pt CMP processes will be of the greatest commercial interest.
A damascene integrated circuit electrode for ferroelectric capacitor structures is also provided. The damascene electrode structure comprises a dielectric layer having a top surface along a horizontal plane and a vertical thickness extending from the dielectric top surface to a first horizontal level in the dielectric layer. The dielectric layer includes an inlay formed from the dielectric top surface, through the vertical thickness, to the dielectric first level. A noble metal electrode, with a roughness of approximately 15 nanometers (nm) and a top surface in alignment with the first plane, fills the dielectric inlay from the dielectric top surface to the dielectric first level. In this manner, the noble metal electrode through the dielectric layer. Dual damascene interconnect structures, with noble metal electrodes, are also provided.